The present invention relates to a circuit design, and more particularly, to a core voltage generator for a semiconductor memory device.
Semiconductor memory devices are used for data storage in various application fields. Desktop computers, laptop computers, and other portable terminals require high-capacity, high-speed, small-sized, low-power semiconductor memory devices.
A method of minimizing current consumption at a core area of a semiconductor memory device has been introduced to provide a low-power semiconductor memory device. Memory cells, bit lines, and word lines are arranged in a core area of the semiconductor memory device, and the core area is designed based on an ultra-fine design rule. The power supply voltage level should be low for operating semiconductor memory devices having ultra-fine patterns at high frequencies.
Semiconductor memory devices are operated by an internal power supply voltage generated using an external power supply voltage. For example, a core voltage (VCORE) is used to access cell data in a dynamic random access memory (DRAM) having a bit line sense amplifier.
When a word line is activated, data stored in memory cells connected to the word line are transferred to bit lines, and bit line sense amplifiers sense and amplify voltage differences of the bit line pairs. In this way, when several thousands of bit line sense amplifiers operate simultaneously, a pull-up power supply line is used and a large amount of current is consumed thro
ugh a core voltage output terminal.
FIG. 1 is a circuit diagram illustrating a conventional core voltage generator.
Referring to FIG. 1, the conventional core voltage generator includes a comparison unit 10, an amplification unit 12, and a half core voltage generation unit 14. The comparison unit 10 compares a half core voltage HF_VCORE with a reference voltage VREFC. The half core voltage HF_VCORE has half the voltage level of a core voltage output terminal, and the reference voltage VREFC has half the level of a target core voltage (1.5 V/2=0.75 V). The amplification unit 12 generates an amplified core voltage of about 1.5 V in response to an output signal of the comparison unit 10. The half core voltage generation unit 14 distributes the core voltage generated from the amplification unit 12 and generates the half core voltage HF_VCORE having half the voltage level of the core voltage output terminal so as to maintain the core voltage VCORE output from the amplification unit 12 at a desired level. The conventional core voltage generator further includes a control switch unit 16 for controlling the operation of the comparison unit 10.
The comparison unit 10 operates when a high-level active enable signal ACTIVE_ENABLE of about 0.830 V is applied to a gate terminal of an n-channel metal oxide semiconductor (NMOS) transistor MN2 of the control switch unit 16.
If the NMOS transistor MN2 is turned on by the high-level active enable signal ACTIVE_ENABLE, an NMOS transistor MN0 is turned on by the reference voltage VREFC, which is applied to the NMOS transistor MN0 from an external voltage source. Thus, drain voltages of the NMOS transistors MN0 and MN2 are reduced. That is, the voltage level of a node N1 is reduced. As a result, a low level signal is applied to a gate terminal of a p-channel metal oxide semiconductor (PMOS) transistor MP2 of the amplification unit 12 to turn on the PMOS transistor MP2. When the PMOS transistor MP2 is turned on by the low level signal, the voltage level of a core voltage VCORE output from the amplification unit 12 increases.
If the core voltage VCORE increases, the half core voltage HF_VCORE output from the half core voltage generation unit 14 also increases, and thus an NMOS transistor MN1 is turned on. Then, the voltage level of a node N2 is reduced. That is, voltage levels of gate terminals of PMOS transistors MP0 and MP1 are reduced. Therefore, the PMOS transistors MP0 and MP1 are turned on. As the PMOS transistors MP0 and MP1 are turned on, the voltage level of the node N1 gradually increases. Therefore, the voltage level of the gate terminal of the PMOS transistor MP2 gradually increases. These operations are repeated until the half core voltage HF_VCORE becomes equal to the reference voltage VREFC.
Meanwhile, when a low-level active disable signal lower than the threshold voltage of the NMOS transistor MN2 is applied to the gate terminal of the NMOS transistor MN2, the control switch unit 16 is turned off and thus the core voltage VCORE is not generated.
If the NMOS transistor MN2 is turned off by the low-level active disable signal, the NMOS transistor MN0 is also turned off because a current path is not formed through the NMOS transistor MN0. Therefore, the voltage level of the node N1 becomes high, and thus, the PMOS transistor MP2 is turned off. That is, the core voltage VCORE is not generated through node N3.
However, the conventional core voltage generator has the following limitations. Although the PMOS transistor MP2 is turned off to interrupt the core voltage VCORE, a small amount of current flows through the PMOS transistor MP2 because NMOS transistors MN3 and MN4 of the half core voltage generation unit 14 are connected between the PMOS transistor MP2 and ground. In other words, as the NMOS transistors MN3 and MN4 used for generating the half core voltage HF_VCORE at node N4 are connected between the core voltage output terminal and ground, the conventional core voltage generator consumes unnecessary power even when it does not generates the core voltage VCORE.